The reliability of a gate oxide in an integrated semiconductor component comprising a field effect transistor encounters intrinsic loading limits as scaling progresses, in particular with development of transistors having ever thinner layers and rising operating field strengths despite lower operating voltages.
The statistical nature of the dielectric breakdown of a gate oxide leads to a wider statistical variation of the lifetime of the respective semiconductor component. This means that, particularly when there is a large active area of an electronic chip, as a result of area scaling, the prognosticated lifetime of the semiconductor components is reduced and can no longer be predicted reliably.
Moreover, in the case of a thin dielectric, a dielectric breakdown is characterized by a significantly smaller rise in the leakage current than in the case of a thicker dielectric layer. In many circuitry applications, the only small rise in the leakage current leads merely to an increase in the power loss in the electronic circuit, but not necessarily to a malfunction, that is to say to a failure of the entire electronic circuit.
Customary test methods for testing an electronic circuit assess the first small alteration of the gate current flowing through the gate oxide, but not the actually relevant malfunction of the electronic circuit or of the electronic switching circuit in the respectively relevant switching circuit environment.
Furthermore, it is known to determine the reliability of a dielectric by means of accelerated test methods on a test structure having a parallel circuit formed by a plurality of identical basic elements. In the case of a thin dielectric, the maximum number of basic elements is limited by the high leakage current that occurs on account of direct tunneling and the small breakdown current.
A breakdown event must lead to a significant current rise above the basic level of the loading current of the electronic switching circuit, also referred to hereinafter as the stress current of the electronic switching circuit, in order to be identified sufficiently dependably.
In the case of a dielectric having a thickness of 2.0 nm, the maximum active area of the entire test structure is restricted to 200 μm2 to 1000 μm2 in accordance with the prior art.
The area limitation that occurs for a test structure leads to a significantly restricted resolution of the defect density and, associated with this, to an increased uncertainty in an extrapolation to reliability requirements (reliability targets) under operating conditions of an electronic switching circuit.
Improving the resolution of the defect density leads to a considerable additional expenditure in the form of required measurement time and/or required equipment for the parallel measurement.
Articles by Kazer et al. describe that, in the case of a thin gate oxide in the case of transistors in an electronic switching circuit, the failure of one or more transistors in the electronic switching circuit on account of a breakdown occurring in the respective gate oxide of a field effect transistor need not yet necessarily lead to the failure of the operativeness of the entire electronic switching circuit compared with the desired function of the electronic switching circuit. (B. Kaczer et al., Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability, IEEE Transactions on Electron Devices, Volume 49, No. 3, pages 500 to 505, March 2002). (B. Kaczer et al., Impact of MOSFET oxide breakdown on digital circuit operation and reliability, IEDM 00, pages 553 to 556, 2000).
The Kazer et al. articles describe in this context a ring oscillator structure comprising 47 inverters connected to form a ring, an inverter being embodied as a NAND gate. A frequency divider switching circuit is connected downstream of the ring oscillator. The switching circuit arrangement comprising ring oscillator and frequency divider switching circuit would be exposed to a loading by application of an electrical voltage and the behavior of the function of the switching circuit arrangement would be examined.
An article by R. Rodriguez et al. describes the influence of a gate oxide breakdown in the case of a field effect transistor in an SRAM memory cell (Static Random Access Memory cell). (R. Rodriguez et al, The impact of gate-oxide breakdown on SRAM stability, IEEE Electron Device Letters, Volume 23, No. 9, pages 559 to 561, September 2002).
Furthermore, an additional article by R. Rodriguez et al. discloses that in the case of an inverter which has an NMOS field effect transistor and a PMOS field effect transistor and is loaded by a voltage, the degradation of the inverter dependent on the polarity of the applied stress voltage. Depending on the polarity of the applied stress voltage, either the respective NMOS field effect transistor or the respective PMOS transistor is loaded to a greater extent and destroyed earlier. (R. Rodriguez et al, A model for gate-oxide breakdown in CMOS in Inverters, IEEE Electron Device Letters, Volume 24, No. 2, pages 114 to 116, February 2003).
Furthermore, an article by B. P. Linder describes an NMOS field effect transistor to be tested, with a gate oxide having a layer thickness of 1.7 nm, to the gate terminal of which is connected a PMOS field effect transistor with a thicker gate oxide. The stress voltage is applied to the drain terminal of the PMOS field effect transistor. (B. P. Linder, Transistor-Limited constant voltage stress of gate dielectrics, Symposium on VLSI Technology Digest of Technical Papers, pages 93 to 94, 2001).
In the case of the circuit comprising two field effect transistors as described by B. P. Linder, given a stress voltage of 3.4 volts and a current driver capability of less than 200 μA, a leakage current that was lower than 100 μA was measured after the gate oxide had undergone breakdown in the NMOS field effect transistor. It should be noted in this context that only the behavior of the gate oxide in the NMOS field effect transistor was examined in isolated fashion upon application of the stress voltage to the PMOS field effect transistor.
German patent No. DE 29 05 271 A1 discloses an integrated circuit arrangement using MOS technology comprising field effect transistors, which has a circuit arrangement for rapidly testing different blocks of the switching circuit. Said circuit arrangement has three transistor switch groups. A first transistor switch group is used for testing an input block. A second transistor switch group serves for turning on and turning off the input block and an output block so that the blocks can be tested jointly and a third block for testing the output block.
German patent No. DE 38 86 722 T2 discloses an electrically erasable and programmable read-only memory comprising a NAND cell structure, said memory having memory cells (M) arranged on an N-type substrate. The memory cells are divided into NAND cell blocks each having series-connected memory cell transistor arrays (M1 to M4). Each of the transistors has a floating gate (50), a control gate connected to a word line (WLi), and an N-type diffusion layer (68, 70), serving as corresponding sources and drains.